View UPD16655N-XXX_2862675.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. mos integrated circuit m m m m pd16655 240-output tft-lcd gate driver 1998 ? document no. s11950ej2v0ds00 (2nd edition) date published february 1999 ns cp(k) printed in japan data sheet the mark shows major revised points. the m pd16655 is a tft-lcd gate driver equipped with 240-output lines. it can output a high-gate scanning voltage in response to 5 v/3.3 v cmos level input because it provided with a level-shift circuit as a logic-input circuit. this gate driver is also provided with an output enable (oe) function, so that drivers can be installed at both sides. features ? high-output voltage (v dd -v ee = amplitude: 31 v max.) ? shift-direction select function ? level shift of negative voltage v ee2 (level shift range: v dd -v ee2 = 15 v) ? 5 v/3.3 v cmos level interface ? output enable function ? as many as 240-output lines ? slim tcp ordering information part number package m pd16655n- xxx tcp(tab pack age) remark the tcps external shape is custom model. to order your tcps external shape, please contact a nec salesperson.
data sheet s11950ej2v0ds00 2 m m m m pd16655 1. block diagram ls note o 1 sr1 ls note ls note clk stvr stvl oe o 2 sr2 o 3 sr3 o 239 sr239 o 240 sr240 240-bit shift register ls note o 238 sr238 ls note r,/l v ee1 v ee2 note ls (level shifter): shifts 5 v/3.3 v cmos level and v dd2 -v ee1 level. remark /xxx indicates active low signal.
data sheet s11950ej2v0ds00 3 m m m m pd16655 2. pin configuration ( m m m m pd16655n-xxx) copper foil surface o 240 o 239 o 238 o 3 o 2 o 1 v dd2 v dd1 stvl oe clk r,/l v cc v ss stvr v ee1 v ee2 remark this figure does not specify the tcp package.
data sheet s11950ej2v0ds00 4 m m m m pd16655 3. pin functions symbol pin name i/o description o 1 to o 240 driver output these pins output scan signals that drive the vertical direction (gate lines) of a tft-lcd. the output signals change in synchronization with the rising edge of shift clock clk. the driver output amplitude is v dd2 - v ee2 . v ss /v cc or v dd1 /v ee1 (input) this is the input of the internal shift register. the input date is read at the rising edge of shift clock clk, and scan signals are output from the o 1 through o 120 pins. the input level is a v cc /v ss or v dd1 - v ee1 level. stvr stvl start pulse input/output v dd1 /v ee1 (output) this pin outputs a start pulse to the m pd16655 at the next stage when two or more m pd16655s are connected in cascade. the pulse is output at the falling edge of the 240th clock of shift clock clk, and is cleared at the falling edge of the 241st clock. r,/l shift direction select input v ss /v cc or v dd1 /v ee1 r,/l = h (right shift): stvr ? o 1 ? o 240 ? stvl r,/l = l (left shift): stvl ? o 240 ? o 1 ? stvr clk shift clock input v ss /v cc this pin inputs a shift clock to the internal shift register. the shift operation is performed in synchronization with the rising edge of this input. oe output enable input v ss /v cc when this pin goes h, the driver output is fixed to l. the shift register is not cleared, however. the internal logic operates even when oe = h. oe is in asynchronization with the clock. v dd1 logic positive power supply 10 v to 25 v v dd2 driver positive power supply 10 v to 25 v v cc reference positive power supply 3.0 to 5.5 v reference voltage to level shifter ls. v ss reference negative power supply connect this pin to the ground of the system. v ee1 logic negative power supply C21 v to C3 v v ee2 driver negative power supply C21 v to v dd2 C 15 v cautions 1. to prevent latch up, turn on power to v cc , v ee1 -v ee2 , v dd1 -v dd2 , and logic input in this order. turn off power in the reverse order. these power up/down sequence must be observed also during transition period. 2. insert a capacitor of about 0.1 m m m m f between each power line, as shown below, to secure noise margin such as v ih and v il , because the internal logic operates on a high voltage level. (v dd = v dd1 = v dd2 ) v dd v cc 0.1 f v ss v ee 0.1 f 0.1 f
data sheet s11950ej2v0ds00 5 m m m m pd16655 3. in an application where the v ee power supply is not shifted, short-circuit v ee2 (driver power) and v ee1 (logic power) outside the tcp. fix unused pins to the v ee level. 4. the level shift range of v ee2 must be v ee1 v ee2 v dd C 15 v. note that, in this case, the guaranteed values of the output on resistance and output fall time slightly change. (v dd = v dd1 = v dd2 ) 5. timing chart clk 1 o 3 o 239 o 240 stvl (stvr) o 1 of next stage o 2 of next stage 23 239 240 241 242 o 1 stvr (stvl) o 2 caution do not use a sequence in which the outputs change all at once because such a sequence may cause malfunctioning.
data sheet s11950ej2v0ds00 6 m m m m pd16655 6. electrical specification absolute maximum ratings (t a = 25c, v ss = 0 v) parameter symbol ratings unit logic positive supply voltage v dd1 C0.5 to +28 v driver positive supply voltage v dd2 C0.5 to +28 v reference positive power supply voltage v cc C0.5 to +7 v power supply voltage v dd1 -v ee1 v dd2 -v ee2 C0.5 to +33 v logic negative supply voltage v ee1 C23 to +0.5 v driver negative supply voltage v ee2 C23 to +0.5 v input voltage v i v ee1 C 0.5 to v dd1 + 0.5 v input current i i 10 ma output current i o 10 ma operating temperature range t a C30 to +85 c storage temperature range t stg C55 to +125 c caution if the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. be sure to use the product within the range of the absolute maximum ratings. recommended operating range (t a = C30 to 85c, v ss = 0 v) parameter symbol min. typ. max. unit logic positive supply voltage v dd1 10 25 v driver positive supply voltage v dd2 10 25 v logic negative supply voltage v ee1 C21 C3 v driver negative supply voltage v ee2 C21 v dd2 C 15 v power supply voltage v dd1 -v ee1 v dd2 -v ee2 15 31 v reference positive power supply voltage v cc 2.7 5.5 v caution observe the following condition when shifting v ee2 (driver power). note that, in this case, the guaranteed values of the output on resistance and output fall time slightly change. v ee1 v ee2 v dd C 15 v (v dd1 or v dd2 )
data sheet s11950ej2v0ds00 7 m m m m pd16655 electrical characteristics (t a = C30 to +85 c, v dd1 = v dd2 = 22 v, v ee1 = v ee2 = C9 v, v ss = 0 v, v cc = 2.7 v or 5.5 v) parameter symbol condition min typ. max. unit high-level input voltage v ih 0.7 v cc v dd1 v low-level input voltage v il v ee1 0.3 v cc v high-level output voltage v oh stvr-stvl, without load v dd1 C 0.05 v dd1 v low-level output voltage v ol stvr-stvl, without load v ee1 v ee1 + 0.05 v high-level output driver current i xoh driver output, v o = v dd2 C 1.0 v C2.0 ma i xol1 driver output, v o = v ee2 + 1.0 v 2.0 ma low-level output driver current i xol2 driver output, v o = v ee2 + 1.0 v, v ee2 = v dd C 15 v 1.5 ma r on1 v o = v ee2 + 1.0 v, v dd2 C 1.0 v 500 w lcd driver output on resistance r on2 v o = v ee2 + 1.0 v, v dd2 C 1.0 v, v ee2 = v dd C 15 v 700 w high-level output pulse current i poh stvr-stvl, v o = v dd1 C 1.0 v C2.0 ma low-level output pulse current i pol stvr-stvl, v o = v ee1 + 1.0 v 2.0 ma input leak current i il v i = 0 v or 3 v or 5 v 1 m a i dd v dd1 , v dd2 pin, f clk = 31.5 khz 400 800 m a i ee v ee1 , v ee2 pin, f clk = 31.5 khz C400 C800 m a static current dissipation i cc v cc pin, f clk = 31.5 khz 50 m a
data sheet s11950ej2v0ds00 8 m m m m pd16655 swiching characteristics (t a = C30 to +85 c, v dd1 = v dd2 = 22 v, v ee1 = v ee2 = C9 v, v ss = 0 v, v cc = 2.7 v to 5.5 v) parameter symbol condition min. typ. max. unit t phl1 600 ns cascade output delay time t plh1 c l = 20 pf 600 ns t phl2 700 ns t plh2 c l = 220 pf clk ? x on 700 ns t d1 700 ns driver output delay time t d2 c l = 220 pf, oe: l ? h c l = 220 pf, oe: h ? l 700 ns output rise time t tlh c l = 220 pf 300 ns t thl1 c l = 220 pf 300 ns output fall time t thl2 c l = 220 pf, v ee2 = v dd C 15 v 400 ns input capacitance c i t a = 25c 15 pf clock frequency f clk in cascade connection 100 khz timing requirements (t a = C30 to 85 c, v dd1 = v dd2 = 22 v, v ee1 = v ee2 = C9 v, v ss = 0 v, v cc = 2.7 v to 5.5 v) parameter symbol condition min. typ. max. unit clock pulse width pw clk 1000 ns data setup time t setup stvr(stvl) - ? clk - 100 ns data hold time t hold clk - ? stvr(stvl) 100 ns caution keep the time and fall time of the logic input to t r = t f = 20 ns (10 to 90 % of the rated values).
data sheet s11950ej2v0ds00 9 m m m m pd16655 7. switching characteristic waveform t setup clk stvr t r 90% 10% t hold pw clk t f 1 237 238 23 t plh2 o 1 t phl2 o 2 o 239 o 240 t plh1 stvl t phl1 oe t d1 o 1-240 t d2 4 5 6 7 239 240 ? ? ? 90% 10% t tlh t thl
data sheet s11950ej2v0ds00 10 m m m m pd16655 8. recommended soldering conditions the following conditions must be met for mounting conditions of the m pd16655. for more details, refer to the semiconductor device mounting technology manual (c10535e). please consult with our sales offices in case other mounting process is used, or in case the mounting is done under different conditions. m m m m pd16655n-xxx : tcp(tab package) mounting condition mounting method condition soldering heating tool 300 to 350c, heating for 2 to 3 seconds: pressure 100 g (per solder) thermocompression acf (adhesive conductive film) temporary bonding 70 to 100c; pressure 3 to 8 kg/cm 2 ; time 3 to 5 secs. real bonding 165 to 180c; pressure 25 to 45 kg/cm 2 , time 30 to 40 secs. (when using the anisotropy conductive film sumizac1003 of sumitomo bakelite, ltd.) caution to find out the detailed conditions for mounting the acf part, please contact the acf manufacturing company. be sure to avoid using two or more mounting methods at a time.
data sheet s11950ej2v0ds00 11 m m m m pd16655 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m m m m pd16655 reference documents nec semiconductor device reliability / quality control system (c10983e) quality grades to necs semiconductor devices (c11531e) the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. ? no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. ? nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. ? descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. ? while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. ? nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98. 8

▲Up To Search▲

Price & Availability of UPD16655N-XXX

	To Download UPD16655N-XXX Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .